Abstract: ADS-B(automatic dependent surveillance broadcast)system is based on Mode S data link, which is widely used in the field of air traffic management owing to its low cost and high precision. However, ADS-B is vulnerable to interference. The very severe overlapping Mode A/C False FRUIT (replies unsynchronized to interrogator transmission)environment leads to bit errors of ADS-B signal. In order to solve this problem, an improved signal correction method is presented combining with serial operation characteristics and resource allocation of FPGA,CRC (cyclic redundancy check)and bit confidence for ADS-B signal. This method is designed and tested by FPGA platform. ADS-B signal test results of FPGA platform show that this improved method needs less hardware consumption and can improve signal processing speed without affecting the performance of error correction,ensuring the transmission reliability of ADS-B signal and making correction rate reaches 100%.

Key words: ADS-B System, CRC checkout, bit confidence, correction, FPGA